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features ? compatible with mcs-51 ? products 12k bytes of in-system reprogra mmable downloadable flash memory ? spi serial interface for program downloading ? endurance: 1,000 write/erase cycles 4v to 6v operating range fully static operation: 0 hz to 24 mhz three-level program memory lock 256 x 8-bit internal ram 32 programmable i/o lines three 16-bit timer/counters nine interrupt sources programmable uart serial channel spi serial interface low-power idle and power-down modes interrupt recovery from power-down programmable watchdog timer dual data pointer power-off flag description the at89s53 is a low-power, high-performance cmos 8-bit microcomputer with 12k bytes of downloadable flash programmable and erasable read only memory. the device is manufactured using atmel?s high-density nonvolatile memory technology and is compatible with the industry-standard 80c51 instruction set and pinout. the on- chip downloadable flash allows the program memory to be reprogrammed in-system through an spi serial interface or by a conventional nonvolatile memory programmer. by combining a versatile 8-bit cpu with downloadable flash on a monolithic chip, the atmel at89s53 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. the at89s53 provides the following standard features: 12k bytes of downloadable flash, 256 bytes of ram, 32 i/o lines, programmable watchdog timer, two data point - ers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and cl ock circuitry. in addition, the at89s53 is designed with static logic for operation down to zero frequency and supports two soft - ware selectable power saving modes. the id le mode stops the cp u while allowing the ram, timer/counters, serial port, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. the downloadable flash can change a single byte at a time and is accessible through the spi serial interface. ho lding reset active forces t he spi bus into a serial pro - gramming interface and allows the program memory to be written to or read from unless lock bit 2 has been activated. 8-bit microcontroller with 12k bytes flash at89s53 not recommended for new designs. use at89s8253. 0787e?micro?3/06
at89s53 0787e?micro?3/06 2 pin description vcc supply voltage. gnd ground. port 0 port 0 is an 8-bit open drain bidirectional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high- impedance inputs. port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external program and data memory. in this mode, p0 has internal pullups. port 0 also receives the code bytes during flash program - ming and outputs the code bytes during program verification. external pullups are required during program verification. port 1 port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (i il ) because of the internal pullups. pin configurations pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (t2) p1.0 (t2 ex) p1.1 p1.2 p1.3 (ss) p1.4 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) plcc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 p1.4 (ss) p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) tqfp 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 (ss) p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd gnd (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4
3 0787e?micro?3/06 at89s53 block diagram port 2 drivers port 2 latch p2.0 - p2.7 flash port 0 latch ram program address register buffer pc incrementer program counter dptr instruction register b register interrupt, serial port, and timer blocks stack pointer acc tmp2 tmp1 alu psw timing and control port 1 drivers p1.0 - p1.7 port 3 latch port 3 drivers p3.0 - p3.7 osc gnd v cc psen ale/prog ea / v pp rst ram addr. register port 0 drivers p0.0 - p0.7 port 1 latch watch dog spi port program logic
at89s53 0787e?micro?3/06 4 some port 1 pins provide additional functions. p1.0 and p1.1 can be configured to be the timer/counter 2 external count input (p1.0/t2) and the timer/counter 2 trigger input (p1.1/t2ex), respectively. pin description furthermore, p1.4, p1.5, p1.6, and p1.7 can be configured as the spi slave port select, data input/output and shift clock input/output pins as shown in the following table. port 1 also receives the low-order address bytes during flash programming and verification. port 2 port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 output buffers can sink/source four ttl inputs. when 1s are written to port 2 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (i il ) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @ dptr). in this application, port 2 uses strong internal pul - lups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash programming and verification. port 3 port 3 is an 8 bit bidirectional i/o port with internal pullups. the port 3 output buffers can sink/source four ttl inputs. when 1s are written to port 3 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il ) because of the pullups. port 3 also serves the function s of various special features of the at89s53, as shown in the following table. port 3 also receives some control signals for flash pro - gramming and verification. rst reset input. a high on this pin for two machine cycles while the oscillator is runnin g resets the device. ale/ prog address latch enable is an output pulse for latching the low byte of the address during accesses to external mem - ory. this pin is also the program pulse input ( prog ) during flash programming. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external tim - ing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only dur - ing a movx or movc instruct ion. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode. psen program store enable is the read strobe to external pro - gram memory. when the at89s53 is executi ng code from external pro - gram memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. port pin alternate functions p1.0 t2 (external count input to timer/counter 2), clock-out p1.1 t2ex (timer/counter 2 capture/reload trigger and direction control) p1.4 ss (slave port select input) p1.5 mosi (master data output, slave data input pin for spi channel) p1.6 miso (master data input, slave data output pin for spi channel) p1.7 sck (master clock output, slave clock input pin for spi channel) port pin alternate functions p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe)
5 at89s53 0787e?micro?3/06 ea /vpp external access enable. ea must be strapped to gnd in order to enable the device to fetch code from external pro - gram memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latc hed on reset. ea should be strapped to v cc for internal program execu - tions. this pin also receives the 12-volt programming enable voltage (v pp ) during flash programming when 12- volt programming is selected. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from th e inverting osc illator amplifier. table 1. at89s53 sfr map and reset values 0f8h 0ffh 0f0h b 00000000 0f7h 0e8h 0efh 0e0h acc 00000000 0e7h 0d8h 0dfh 0d0h psw 00000000 spcr 000001xx 0d7h 0c8h t2con 00000000 t2mod xxxxxx00 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 0cfh 0c0h 0c7h 0b8h ip xx000000 0bfh 0b0h p3 11111111 0b7h 0a8h ie 0x000000 spsr 00xxxxxx 0afh 0a0h p2 11111111 0a7h 98h scon 00000000 sbuf xxxxxxxx 9fh 90h p1 11111111 wcon 00000010 97h 88h tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 8fh 80h p0 11111111 sp 00000111 dp0l 00000000 dp0h 00000000 dp1l 00000000 dp1h 00000000 spdr xxxxxxxx pcon 0xxx0000 87h
6 0787e?micro?3/06 at89s53 special function registers a map of the on-chip memory area called the special func - tion register (sfr) space is shown in table 1 . note that not all of the addresses are occupied, and unoc - cupied addresses may not be implemented on the chip. read accesses to these addre sses will in general return random data, and write acce sses will have an indeterminate effect. user software should not write 1s to these unlisted loca - tions, since they may be used in future products to invoke new features. in that case, the reset or inactive values of the new bits will always be 0. timer 2 registers control and status bits are contained in registers t2con (shown in table 2 ) and t2mod (shown in table 9 ) for timer 2. the register pair (rcap2h, rcap2l) are the capture/reload registers for timer 2 in 16-bit cap - ture mode or 16-bit auto-reload mode. watchdog control register the wcon register contains control bits for the watchdog timer (shown in table 3 ). the dps bit selects one of two dptr registers available. table 2. t2con?timer/counter 2 control register t2con address = 0c8h reset value = 0000 0000b bit addressable tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 bit 7 6 5 4 3 2 1 0 symbol function tf2 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk = 1 or tclk = 1. exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk receive clock enable. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. rclk = 0 causes timer 1 overflows to be used for the receive clock. tclk transmit clock enable. when set, causes the serial port to us e timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 timer 2 external enable. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 start/stop control for timer 2. tr2 = 1 starts the timer. c/ t2 timer or counter select for timer 2. c/ t2 = 0 for timer function. c/ t2 = 1 for external event counter (falling edge triggered). cp/ rl2 capture/reload select. cp/ rl2 = 1 causes captures to occur on negativ e transitions at t2ex if exen2 = 1. cp/ rl2 = 0 causes automatic reloads to oc cur when timer 2 overflows or negative transitions occur at t2ex when exen2 = 1. when either rclk or tclk = 1, this bit is ignored and t he timer is forced to auto-reload on timer 2 overflow.
7 0787e?micro?3/06 at89s53 spi registers control and status bits for the serial periph - eral interface are contained in registers spcr (shown in table 4 ) and spsr (shown in table 5 ). the spi data bits are contained in the spdr register. writing the spi data register during serial data transfer sets the write collision bit, wcol, in the spsr regist er. the spdr is double buff - ered for writing and the values in spdr are not changed by reset. interrupt registers the global interrupt enable bit and the individual interrupt enable bits are in the ie register. in addition, the individual interrupt enable bit for the spi is in the spcr register. two priorities can be set for each of the six interrupt sources in the ip register. dual data pointer registers to facilitate accessing exter - nal data memory, two banks of 16-bit data pointer registers are provided: dp0 at sfr address locations 82h-83h and dp1 at 84h-85h. bit dps = 0 in sfr wcon selects dp0 and dps = 1 selects dp1. the user should always initalize the dps bit to the appropriate value before accessing the respective data pointer register. power off flag the power off flag (pof) is located at bit_4 (pcon.4) in the pcon sfr. pof is set to ?1? during power up. it can be set and reset under software control and is not affected by reset. table 3. wcon?watchdog control register wcon address = 96h reset value = 0000 0010b ps2 ps1 ps0 reserved reserved dps wdtrst wdten bit 7 6 5 4 3 2 1 0 symbol function ps2 ps1 ps0 prescaler bits for the watchdog timer. when all three bits are set to ?0?, the watchdog timer has a nominal period of 16 ms. when all three bits are set to ?1?, the nominal period is 2048 ms. dps data pointer register select. dps = 0 selects the first bank of data pointer register, dp0, and dps = 1 selects the second bank, dp1 wdtrst watchdog timer reset. each time this bit is set to ?1? by user software, a pulse is generated to reset the watchdog timer. the wdtrst bit is then automatically reset to ?0? in the next instruction cycle. the wdtrst bit is write-only. wdten watchdog timer enable bit. wdten = 1 enables the watchdog timer and wdten = 0 disables the watchdog timer.
8 0787e?micro?3/06 at89s53 table 4. spcr?spi control register spcr address = d5h reset value = 0000 01xxb spie spe dord mstr cpol cpha spr1 spr0 bit 7 6 5 4 3 2 1 0 symbol function spie spi interrupt enable. this bit, in conjunction with the es bit in the ie register, enables spi interrupts: spie = 1 and es = 1 enable spi interrupts. spie = 0 disables spi interrupts. spe spi enable. spi = 1 enables the spi channel and connects ss , mosi, miso and sck to pi ns p1.4, p1.5, p1.6, and p1.7. spi = 0 disabl es the spi channel. dord data order. dord = 1 selects lsb first data transmi ssion. dord = 0 selects msb first data transmission. mstr master/slave select. mstr = 1 selects master spi mode. mstr = 0 selects slave spi mode. cpol clock polarity. when cpol = 1, sck is high when idle. w hen cpol = 0, sck of the master device is low when not transmitting. please refer to figure on spi clock phase and polarity control. cpha clock phase. the cpha bit together with the cpol bit cont rols the clock and data relationship between master and slave. please refer to figure on spi clock phase and polarity control. spr0 spr1 spi clock rate select. these two bits control the sck rate of the device configured as master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator frequency, f osc. , is as follows: spr1spr0sck = f osc. divided by 004 0116 1064 1 1 128 table 5. spsr?spi status register data memory - ram spsr address = aah reset value = 00xx xxxxb spif wcol ? ? ? ? ? ? bit 7 6 5 4 3 2 1 0 symbol function spif spi interrupt flag. when a serial transfer is complete, t he spif bit is set and an interrupt is generated if spie = 1 and es = 1. the spif bit is cleared by reading the spi status register with spif and wcol bits set, and then accessing the spi data register. wcol write collision flag. the wcol bit is set if the spi data regi ster is written during a data transfer. during data transfer, the result of reading the spdr register may be incorrect, and writing to it has no effect. the wcol bit (and the spif bit) are cleared by reading the spi status register wit h spif and wcol set, and then accessing the spi data register. table 6. spdr?spi data register spdr address = 86h reset value = unchanged spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 bit 7 6 5 4 3 2 1 0
9 at89s53 0787e?micro?3/06 data memory - ram the at89s53 implements 256 bytes of ram. the upper 128 bytes of ram occupy a parallel space to the special function registers. that means the upper 128 bytes have the same addresses as the sfr space but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the address mode used in the instruction specifies whether the cpu a ccesses the upper 128 bytes of ram or the sfr space. instructions that use direct addressing access sfr space. for example, the following direct addressing instruction accesses the sfr at location 0a0h (which is p2). mov 0a0h, #data instructions that use indirect addressing access the upper 128 bytes of ram. for example, the following indirect addressing instruction, where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). mov @r0, #data note that stack operations are examples of indirect addressing, so the upper 128 bytes of data ram are avail - able as stack space. programmable watchdog timer the programmable watchdog timer (wdt) operates from an independent oscillator. the prescaler bits, ps0, ps1 and ps2 in sfr wcon are used to set the period of the watchdog timer from 16 ms to 2048 ms. the available timer periods are shown in the following table and the actual timer periods (at v cc = 5v) are within 30% of the nominal. the wdt is disabled by power-on reset and during power-down. it is enabled by setting the wdten bit in sfr wcon (address = 96h). the wdt is reset by setting the wdtrst bit in wcon. when the wdt times out without being reset or disabled, an internal rst pulse is generated to reset the cpu. timer 0 and 1 timer 0 and timer 1 in the at89s53 operate the same way as timer 0 and timer 1 in the at89c51, at89c52 and at89c55. for further information, see the october 1995 microcontroller data book, page 2-45, section titled, ?timer/counters.? timer 2 timer 2 is a 16-bit timer/counter that can operate as either a timer or an event counter. the type of operation is selected by bit c/ t2 in the sfr t2con (shown in table 2 ). timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. the modes are selected by bits in t2con, as shown in table 8 . timer 2 consists of two 8-bit registers, th2 and tl2. in the timer function, the tl2 register is incremented every machine cycle. since a machine cycle consists of 12 oscil - lator periods, the count rate is 1/12 of the oscillator frequency. in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t2. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the c ycle following the one in which the transition was detected. since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transi - tion, the maximum count rate is 1/24 of the oscillator frequency. to ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. table 7. watchdog timer period selection wdt prescaler bits period (nominal) ps2 ps1 ps0 0 0 0 16 ms 0 0 1 32 ms 0 1 0 64 ms 0 1 1 128 ms 1 0 0 256 ms 1 0 1 512 ms 1 1 0 1024 ms 1 1 1 2048 ms table 8. timer 2 operating modes rclk + tclk cp/ rl2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 (off) table 7. watchdog timer period selection
at89s53 0787e?micro?3/06 10 capture mode in the capture mode, two options are selected by bit exen2 in t2con. if exen2 = 0, timer 2 is a 16-bit timer or counter which upon overflow sets bit tf2 in t2con. this bit can then be used to generate an interrupt. if exen2 = 1, timer 2 performs the same operation, but a l- to-0 transition at external input t2ex also causes the current value in th2 and tl2 to be captured into rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set. the exf2 bit, like tf2, can generate an interrupt. the capture mode is illustrated in figure 1 . figure 1. timer 2 in capture mode auto-reload (up or down counter) timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. this feature is invoked by the dcen (down counter enable) bit located in the sfr t2mod (see table 9 ). upon reset, the dcen bit is set to 0 so that timer 2 will default to count up. when dcen is set, timer 2 can count up or down, depending on the value of the t2ex pin. figure 2 shows timer 2 automatically counting up when dcen = 0. in this mode, two options are selected by bit exen2 in t2con. if exen2 = 0, timer 2 counts up to 0ffffh and then sets the tf2 bit upon overflow. the over - flow also causes the timer registers to be reloaded with the 16-bit value in rcap2h and rcap2l. the values in rcap2h and rcap2l are preset by software. if exen2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input t2ex. this transition also sets the exf2 bit. both the tf2 and exf2 bits can generate an interrupt if enabled. setting the dcen bit enables timer 2 to count up or down, as shown in figure 3 . in this mode, the t2ex pin controls the direction of the count. a logic 1 at t2ex makes timer 2 count up. the timer will overfl ow at 0ffffh and set the tf2 bit. this overflow also causes the 16-bit value in rcap2h and rcap2l to be reloaded into the timer regis - ters, th2 and tl2, respectively. a logic 0 at t2ex makes timer 2 count down. the timer underflows when th2 and tl2 equal the values stored in rcap2h and rcap2l. the underflow sets the tf2 bit and causes 0ffffh to be reloaded into the timer registers. the exf2 bit toggles whenever timer 2 overflows or underflows and can be used as a 17th bit of resolution. in this operating mode, exf2 does not flag an interrupt. osc exf2 t2ex pin t2 pin tr2 exen2 c/t2 = 0 c/t2 = 1 control capture overflow control transition detector timer 2 interrupt 12 rcap2l rcap2h th2 tl2 tf2
11 0787e?micro?3/06 at89s53 figure 2. timer 2 in auto reload mode (dcen = 0) table 9. t2mod?timer 2 mode control register t2mod address = 0c9h reset value = xxxx xx00b not bit addressable ? ? ? ? ? ? t2oe dcen bit 7 6 5 4 3 2 1 0 symbol function ? not implemented, reserved for future use. t2oe timer 2 output enable bit. dcen when set, this bit allows timer 2 to be configured as an up/down counter.
12 0787e?micro?3/06 at89s53 figure 3. timer 2 auto reload mode (dcen = 1) figure 4. timer 2 in baud rate generator mode osc smod1 rclk tclk rx clock tx clock t2ex pin t2 pin tr2 control "1" "1" "1" "0" "0" "0" timer 1 overflow note: osc. freq. is divided by 2, not 12 timer 2 interrupt 2 2 16 16 rcap2l rcap2h th2 tl2 c/t2 = 0 c/t2 = 1 exf2 control transition detector exen2
13 at89s53 0787e?micro?3/06 baud rate generator timer 2 is selected as the baud rate generator by setting tclk and/or rclk in t2con ( table 2 ). note that the baud rates for transmit and receive can be different if timer 2 is used for the receiver or transmitter and timer 1 is used for the other function. setting rclk and/or tclk puts timer 2 into its baud rate generator mode, as shown in figure 4 . the baud rate generator mode is similar to the auto-reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2?s overflow rate according to the following equation. the timer can be configured for either timer or counter operation. in most applications, it is configured for timer operation (cp/ t2 = 0). the timer operation is different for timer 2 when it is used as a baud rate generator. normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). as a baud rate gene rator, however, it increments every state time (at 1/2 the oscillator fre - quency). the baud rate formula is given below. where (rcap2h, rcap2l) is the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. timer 2 as a baud rate generator is shown in figure 4. this figure is valid only if rclk or tclk = 1 in t2con. note that a rollover in th2 does not set tf2 and will not gener - ate an interrupt. note too, that if exen2 is set, a 1-to-0 transition in t2ex will set exf2 but will not cause a reload from (rcap2h, rcap2l) to (t h2, tl2). thus when timer 2 is in use as a baud rate generator, t2ex can be used as an extra external interrupt. note that when timer 2 is running (tr2 = 1) as a timer in the baud rate generator mode, th2 or tl2 should not be read from or written to. under these conditions, the timer is incremented every state time, and the results of a read or write may not be accurate. the rcap2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. programmable clock out a 50% duty cycle clock can be programmed to come out on p1.0, as shown in figure 5 . this pin, besides being a regu - lar i/0 pin, has two alternate functions. it can be programmed to input the external clock for timer/counter 2 or to output a 50% duty cycle clock ranging from 61 hz to 4 mhz at a 16 mhz operating frequency. to configure the timer/counter 2 as a clock generator, bit c/ t2 (t2con.1) must be cleared and bit t2oe (t2mod.1) must be set. bit tr2 (t2con.2) starts and stops the timer. the clock-out frequency depends on the oscillator fre - quency and the reload value of timer 2 capture registers (rcap2h, rcap2l), as shown in the following equation. in the clock-out mode, timer 2 rollovers will not generate an interrupt. this behavior is similar to when timer 2 is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simulta - neously. note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use rcap2h and rcap2l. modes 1 and 3 baud rates timer 2 overflow rate 16 ----------------------------------------------------------- - = modes 1 and 3 baud rate --------------------------------------- oscillator frequency 32 65536 rcap2h,rcap2l () ? [] ---------------------------------------------------------------------------------------------- = clock-out frequency oscillator frequency 4 65536 rcap2h,rcap2l () ? [] ------------------------------------------------------------------------------------------ - =
14 0787e?micro?3/06 at89s53 figure 5. timer 2 in clock-out mode figure 6. spi block diagram oscillator 8/16-bit shift register read data buffer pin control logic spi control spi status register spi interrupt request internal data b u s select spi clock (master) divider 41664128 spi control register 8 8 8 spif wcol spr1 mstr spie clock logic clock msb s m spe dord mstr cpol cpha spr1 spr0 mstr spe dord lsb s m m s miso p1.6 mosi p1.5 sck 1.7 ss p1.4 spr0 spe
15 0787e?micro?3/06 at89s53 uart the uart in the at89s53 operates the same way as the uart in the at89c51, at89c52 and at89c55. for fur - ther information, see the october 1995 microcontroller data book, page 2-49, section titled, ?serial interface.? serial peripheral interface the serial peripheral interfac e (spi) allows high-speed syn - chronous data transfer between the at89s53 and peripheral devices or between several at89s53 devices. the at89s53 spi features include the following: full-duplex, 3-wire synchronous data transfer master or slave operation 1.5 mhz bit frequency (max.) lsb first or msb first data transfer four programmable bit rates end of transmission interrupt flag write collision flag protection wakeup from idle mode (slave mode only) the interconnection between master and slave cpus with spi is shown in the followi ng figure. the sck pin is the clock output in the master mode but is the clock input in the slave mode. writing to the spi data register of the master cpu starts the spi clock generator, and the data written shifts out of the mosi pin and into the mosi pin of the slave cpu. after shifting one byte, the spi clock generator stops, setting the end of transmission flag (spif). if both the spi interrupt enable bit (spie) and the serial port inter - rupt enable bit (es) are set, an interrupt is requested. the slave select input, ss /p1.4, is set low to select an individual spi device as a slave. when ss /p1.4 is set high, the spi port is deactivated and the mosi/p1.5 pin can be used as an input. there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 8 and figure 9 . figure 7. spi master-slave interconnection figure 8. spi transfer format with cpha = 0 *not defined but normally msb of character just received 8-bit shift register master clock generator spi miso 8-bit shift register slave miso mosi mosi sck sck ss ss v cc msb lsb msb lsb
16 0787e?micro?3/06 at89s53 figure 9. spi transfer form at with cpha = 1 *not defined but normally lsb of previously transmitted character interrupts the at89s53 has a total of six interrupt vectors: two exter - nal interrupts ( int0 and int1 ), three timer interrupts (timers 0, 1, and 2), and the serial port interrupt. these interrupts are all shown in figure 10 . each of these interrupt sources can be individually enabled or disabled by setting or cleari ng a bit in special function register ie. ie also contains a global disable bit, ea, which disables all interrupts at once. note that table 10 shows that bit position ie.6 is unimple - mented. in the at89c51, bit position ie.5 is also unimplemented. user software should not write 1s to these bit positions, since they may be used in future at89 products. figure 10. interrupt sources msb 6 5 4 3 2 1 lsb 1 2 3 4 5 6 7 8 msb * 65432 1 lsb sck cycle # (for reference) sck (cpol=0) sck (cpol=1) mosi (from master) miso (from slave) ss (to slave) table 10. interrupt enable (ie) register (msb)(lsb) ea ? et2 es et1 ex1 et0 ex0 enable bit = 1 enables the interrupt. enable bit = 0 disables the interrupt. symbol position function ea ie.7 disables all interrupts. if ea = 0, no interrupt is acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ? ie.6 reserved. et2 ie.5 timer 2 interrupt enable bit. es ie.4 spi and uart interrupt enable bit. et1 ie.3 timer 1 interrupt enable bit. ex1 ie.2 external interrupt 1 enable bit. et0 ie.1 timer 0 interrupt enable bit. ex0 ie.0 external interrupt 0 enable bit. user software should never write 1s to unimplemented bits, because they may be used in future at89 products.
17 at89s53 0787e?micro?3/06 timer 2 interrupt is generated by the logical or of bits tf2 and exf2 in register t2con. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine may have to determine whether it was tf2 or exf2 that generated the interrupt, and that bit will have to be cleared in software. the timer 0 and timer 1 flags, tf0 and tf1, are set at s5p2 of the cycle in which the timers overflow. the values are then polled by the circuitry in the next cycle. however, the timer 2 flag, tf2, is set at s2p2 and is polled in the same cycle in which the timer overflows. oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in figure 11 . either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 sh ould be left unconnected while xtal1 is driven, as shown in figure 12 . there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi - mum voltage high and low time specifications must be observed. figure 11. oscillator connections note: c1, c2 = 30 pf 10 pf for crystals = 40 pf 10 pf for ceramic resonators figure 12. external clock drive configuration
at89s53 0787e?micro?3/06 18 idle mode in idle mode, the cpu puts itself to sleep while all the on- chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the spe - cial functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to in ternal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle mode is termi - nated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to exter - nal memory. power-down mode in the power-down mode, the oscillator is stopped and the instruction that invokes power-down is the last instruction executed. the on-chip ram and special function regis - ters retain their values un til the power-down mode is terminated. exit from power-do wn can be initiated either by a hardware reset or by an enabled external interrupt. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillato r to restart and stabilize. to exit power-down via an interrupt, the external interrupt must be enabled as level sensitive before entering power- down. the interrupt service routine starts at 16 ms (nomi - nal) after the enabled interrupt pin is activated. program memory lock bits the at89s53 has three lock bits that can be left unpro - grammed (u) or can be programmed (p) to obtain the additional features listed in the following table. when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is pow - ered up without a reset, the latc h initializes to a random value and holds that value until reset is activated. the latched value of ea must agree with the current logic level at that pin in order for the device to function properly. once programmed, the lock bits can only be unpro - grammed with the chip erase operations in either the parallel or serial modes. notes: 1. u = unprogrammed 2. p = programmed status of external pins during idle and power-down modes mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data lock bit protection modes (1)(2) program lock bits protection type lb1 lb2 lb3 1 u u u no internal memory lock feature. 2 p u u movc instructions executed from external prog ram memory are disabled from fetching code bytes from internal memory. ea is sampled and latched on reset and further programming of the flash memory (parallel or serial mode) is disabled. 3 p p u same as mode 2, but parallel or serial verify are also disabled. 4 p p p same as mode 3, but external execution is also disabled.
19 at89s53 0787e?micro?3/06 programming the flash atmel?s at89s53 flash microcontroller offers 12k bytes of in-system reprogrammable flash code memory. the at89s53 is normally shipped with the on-chip flash code memory array in the erased state (i.e. contents = ffh) and ready to be programmed. this device supports a high-voltage (12v) parallel pr ogramming mode and a low- voltage (5v) serial programming mode. the serial pro - gramming mode provides a convenient way to download the at89s53 inside the user?s system. the parallel pro - gramming mode is compatible with conventional third party flash or eprom programmers. the code memory array occupies one contiguous address space from 0000h to 2fffh. the code array on the at89s53 is programmed byte-by- byte in either programming mode. an auto-erase cycle is provided with the self-timed programming operation in the serial programming mode. there is no need to perform the chip erase operation to reprogram any memory location in the serial programming mode unless any of the lock bits have been programmed. in the parallel programming mode, there is no auto-erase cycle. to reprogram any non-blank byte, the user needs to use the chip erase operation first to erase the entire code memory array. parallel programming algorithm: to program and verify the at89s53 in the parallel programming mode, the follow - ing sequence is recommended: 1. power-up sequence: apply power between v cc and gnd pins. set rst pin to ?h?. apply a 3 mhz to 24 mhz clock to xtal1 pin and wait for at least 10 milliseconds. 2. set psen pin to ?l? ale pin to ?h? ea pin to ?h? and all other pins to ?h?. 3. apply the appropriate combination of ?h? or ?l? logic levels to pins p2.6, p2.7, p3.6, p3.7 to select one of the programming operations shown in the flash programming modes table. 4. apply the desired byte address to pins p1.0 to p1.7 and p2.0 to p2.5. apply data to pins p0.0 to p0.7 for write code operation. 5. raise ea /v pp to 12v to enable flash programming, erase or verification. 6. pulse ale/ prog once to program a byte in the code memory array, or the lock bits. the byte-write cycle is self-timed and typically takes 1.5 ms. 7. to verify the byte just programmed, bring pin p2.7 to ?l? and read the programmed data at pins p0.0 to p0.7. 8. repeat steps 3 through 7 changing the address and data for the entire 12k-byte array or until the end of the object file is reached. 9. power-off sequence: set xtal1 to ?l?. set rst and ea pins to ?l?. turn v cc power off. data polling: the at89s53 features data polling to indi - cate the end of a write cycle. during a write cycle in the parallel or serial programming mode, an attempted read of the last byte wr itten will result in the complement of the writ - ten datum on p0.7 (parallel mode), and on the msb of the serial output byte on miso (serial mode). once the write cycle has been completed, true data are valid on all out - puts, and the next cycle may begin. data polling may begin any time after a writ e cycle has been initiated. ready/ busy : the progress of byte programming in the parallel programming mode can also be monitored by the rdy/ bsy output signal. pin p3.4 is pulled low after ale goes high during programming to indicate busy . p3.4 is pulled high again when programming is done to indicate ready. program verify: if lock bits lb1 and lb2 have not been programmed, the programmed code can be read back via the address and data lines for verification. the state of the lock bits can also be verified directly in the parallel pro - gramming mode. in the serial programming mode, the state of the lock bits can only be veri fied indirectly by observing that the lock bit features are enabled. chip erase: in the parallel programming mode, chip erase is initiated by using the proper combination of control sig - nals and by holding ale/ prog low for 10 ms. the code array is written with all ?1?s in the chip erase operation. in the serial programming mode, a chip erase operation is initiated by issuing the chip er ase instruction. in this mode, chip erase is self-timed and takes about 16 ms. during chip erase, a serial read from any address location will return 00h at the data outputs. serial programming fuse: a programmable fuse is avail - able to disable serial programming if the user needs maximum system security. the serial programming fuse can only be programmed or erased in the parallel program - ming mode. the at89s53 is shipped with the serial programming mode enabled.
at89s53 0787e?micro?3/06 20 reading the signature bytes: the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p3.6 and p3.7 must be pulled to a logic low. the values returned are as follows: (030h) = 1eh indicates manufactured by atmel (031h) = 53h indicates 89s53 programming interface every code byte in the flash array can be written, and the entire array can be erased, by using the appropriate combi - nation of control signals. the write operation cycle is self- timed and once initiated, will automatically time itself to completion. all major programming vendors offer worldwide support for the atmel microcontroller series. please contact your local programming vendor for the appropriate software revision. serial downloading the code memory array can be programmed using the serial spi bus while rst is pulled to v cc . the serial inter - face consists of pins sck, mosi (input) and miso (output). after rst is set high, the pr ogramming enable instruction needs to be executed first before program/erase operations can be executed. an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction unless any of the lock bits have been programmed. the chip erase opera - tion turns the content of every memory location in the code array into ffh. the code memory array has an address space of 0000h to 2fffh. either an external system clock is supplied at pin xtal1 or a crystal needs to be connected across pins xtal1 and xtal2. the maximum serial clock (sck) frequency should be less than 1/40 of the crystal frequency. with a 24 mhz oscillator clock, the maximum sck frequency is 600 khz. serial programming algorithm to program and verify the at89s53 in the serial program - ming mode, the following sequence is recommended: 1. power-up sequence: apply power between vcc and gnd pins. set rst pin to ?h?. if a crystal is not connected across pins xtal1 and xtal2, apply a 3 mhz to 24 mhz clock to xtal1 pin and wait for at least 10 milliseconds. 2. enable serial programming by sending the pro - gramming enable serial instruction to pin mosi/p1.5. the frequency of the shift clock sup - plied at pin sck/p1.7 needs to be less than the cpu clock at xtal1 divided by 40. 3. the code array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. the selected memory location is first automatically erased before new data is written. the write cycle is self-timed and typ - ically takes less than 2.5 ms at 5v. 4. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso/p1.6. 5. at the end of a programming session, rst can be set low to commence normal operation. power-off sequence (if needed): set xtal1 to ?l? (if a crystal is not used). set rst to ?l?. turn v cc power off. serial programming instruction the instruction set for serial programming follows a 3 byte protocol and is shown in the following table.
21 0787e?micro?3/06 at89s53 . notes: 1. ?h? = weakly pulled ?high? internally. 2. chip erase and serial programming fuse require a 10 ms prog pulse. chip erase needs to be performed first before reprogramming any byte with a content other than ffh. 3. p3.4 is pulled low during programming to indicate rdy /bsy. 4. ?x? = don?t care flash parallel programming modes mode rst psen ale/ prog ea /v pp p2.6 p2.7 p3.6 p3.7 data i/o p0.7:0 address p2.5:0 p1.7:0 serial prog. modes h h (1) h (1) x chip erase h l 12v h l l l x x write (12k bytes) memory h l 12v l h h h din addr read (12k bytes) memory h l h 12v l l h h dout addr write lock bits: h l 12v h l h l din x bit - 1 p0.7 = 0 x bit - 2 p0.6 = 0 x bit - 3 p0.5 = 0 x read lock bits: h l h 12v h h l l dout x bit - 1 @p0.2 x bit - 2 @p0.1 x bit - 3 @p0.0 x read atmel code h l h 12v l l l l dout 30h read device code h l h 12v l l l l dout 31h serial prog. enable h l 12v l h l h p0.0 = 0 x serial prog. disable h l 12v l h l h p0.0 = 1 x read serial prog. fuse h l h 12v h h l h @p0.0 x (2) (2) (2) instruction set notes: 1. data polling is used to indicate the end of a write c ycle which typically takes less than 10 ms at 2.7v. 2. ?x? = don?t care. instruction input format operation byte 1 byte 2 byte 3 programming enable 1010 1100 0101 0011 xxxx xxxx enable serial programming interface after rst goes high. chip erase 1010 1100 xxxx x100 xxxx xxxx chip erase the 12k memory array. read code memory low addr xxxx xxxx read data from code memory array at the selected address. the 6 msbs of the first byte are the high order address bits. the low order address bits are in the second byte. data are available at pin miso during the third byte. write code memory low addr data in write data to code memory location at selected address. the address bits are the 6 msbs of the first byte together with the second byte. write lock bits 1010 1100 xxxx xxxx write lock bits. set lb1, lb2 or lb3 = ?0? to program lock bits. a12 a11 a10 a9 a8 a13 01 a12 a11 a10 a9 a8 a13 10 lb1 lb2 lb3 xx111
at89s53 0787e?micro?3/06 22 figure 13. programming the flash memory figure 14. verifying the flash memory figure 15. flash serial downloading p1 p2.6 p3.6 p2.0 - p2.5 a0 - a7 addr. 0000h/2fffh see flash programming modes table 3-24 mhz a8 - a13 p0 +5v p2.7 pgm data prog v pp v i h ale p3.7 xtal2 ea rst psen xtal1 gnd v cc at89s53 p1 p2.6 p3.6 p2.0 - p2.5 a0 - a7 addr. 0000h/2fffh see flash programming modes table 3-24 mhz a8 - a13 p0 +5v p2.7 pgm data (use 10k pullups) v i h v i h ale p3.7 xtal2 ea rst psen xtal1 gnd v cc at89s53 v pp p1.7/sck data output instruction input clock in 3-24 mhz +4.0v to 6.0v p1.5/mosi v i h xtal2 rst xtal1 gnd v cc at89s53 p1.6/miso
23 0787e?micro?3/06 at89s53 flash programming and verification characteristics ? parallel mode t a = 0c to 70c, v cc = 5.0v 10% symbol parameter min max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 1.0 ma 1/t clcl oscillator frequency 3 24 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 ( enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 s t glgh prog width 1 110 s t avqv address to data valid 48t clcl t elqv enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghbl prog high to busy low 1.0 s t wc byte write cycle time 2.0 ms
24 0787e?micro?3/06 at89s53 flash programming and verificat ion waveforms ? parallel mode serial downloading waveforms serial clock input serial data input sck/p1.7 mosi/p1.5 miso/p1.6 serial data output 0 1 2 3 4 5 6 7 msb msb lsb lsb
25 0787e?micro?3/06 at89s53 notes: 1. under steady state (n on-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1,2, 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. minimum v cc for power-down is 2v. absolute maximum ratings* operating temperature.................................. -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam - age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage ............................................ 6.6v dc output current...................................................... 15.0 ma dc characteristics the values shown in this table are valid for t a = -40c to 85c and v cc = 4.0v to 6.0v, unless otherwise noted symbol parameter condition min max units v il input low-voltage (except ea ) -0.5 0.2 v cc - 0.1 v v il1 input low-voltage ( ea ) -0.5 0.2 v cc - 0.3 v v ih input hight-voltage (except xtal1, rst) 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input hight-voltage (xtal1, rst) 0.7 v cc v cc + 0.5 v v ol output low-voltage (1) (ports 1,2,3) i ol = 1.6 ma 0.5 v v ol1 output low-voltage (1) (port 0, ale, psen ) i ol = 3.2 ma 0.5 v v oh output hight-voltage (ports 1,2,3, ale, psen ) i oh = -60 a, v cc = 5v 10% 2.4 v i oh = -25 a 0.75 v cc v i oh = -10 a 0.9 v cc v v oh1 output hight-voltage (port 0 in external bus mode) i oh = -800 a, v cc = 5v 10% 2.4 v i oh = -300 a 0.75 v cc v i oh = -80 a 0.9 v cc v i il logical 0 input current (ports 1,2,3) v in = 0.45v -50 a i tl logical 1 to 0 transition current (ports 1,2,3) v in = 2v, v cc = 5v 10% -650 a i li input leakage current (port 0, ea ) 0.45 < v in < v cc 10 a rrst reset pull-down resistor 50 300 k ? c io pin capacitance test freq. = 1 mhz, t a = 25c 10 pf i cc power supply current active mode, 12 mhz 25 ma idle mode, 12 mhz 6.5 ma power-down mode (2) v cc = 6v 100 a v cc = 3v 40 a
26 0787e?micro?3/06 at89s53 ac characteristics under operating conditions, load capacitance for port 0, ale/ prog , and psen = 100 pf; load capacitance for all other outputs = 80 pf. external program and data memory characteristics symbol parameter 12mhz oscillator variable oscillator units min max min max 1/t clcl oscillator frequency 0 24 mhz t lhll ale pulse width 127 2t clcl - 40 ns t avll address valid to ale low 43 t clcl - 13 ns t llax address hold after ale low 48 t clcl - 20 ns t lliv ale low to valid instruction in 233 4t clcl - 65 ns t llpl ale low to psen low 43 t clcl - 13 ns t plph psen pulse width 205 3t clcl - 20 ns t pliv psen low to valid instruction in 145 3t clcl - 45 ns t pxix input instruction hold after psen 0 0 ns t pxiz input instruction float after psen 59 t clcl - 10 ns t pxav psen to address valid 75 t clcl - 8 ns t aviv address to valid instruction in 312 5t clcl - 55 ns t plaz psen low to address float 10 10 ns t rlrh rd pulse width 400 6t clcl - 100 ns t wlwh wr pulse width 400 6t clcl - 100 ns t rldv rd low to valid data in 252 5t clcl - 90 ns t rhdx data hold after rd 0 0 ns t rhdz data float after rd 97 2t clcl - 28 ns t lldv ale low to valid data in 517 8t clcl - 150 ns t avdv address to valid data in 585 9t clcl - 165 ns t llwl ale low to rd or wr low 200 300 3t clcl - 50 3t clcl + 50 ns t avwl address to rd or wr low 203 4t clcl - 75 ns t qvwx data valid to wr transition 23 t clcl - 20 ns t qvwh data valid to wr high 433 7t clcl - 120 ns t whqx data hold after wr 33 t clcl - 20 ns t rlaz rd low to address float 0 0 ns t whlh rd or wr high to ale high 43 123 t clcl - 20 t clcl + 25 ns
27 0787e?micro?3/06 at89s53 external program memory read cycle external data memory read cycle
28 0787e?micro?3/06 at89s53 external data memory write cycle external clock drive waveforms external clock drive symbol parameter v cc = 4.0v to 6.0v min max units 1/t clcl oscillator frequency 0 24 mhz t clcl clock period 41.6 ns t chcx high time 15 ns t clcx low time 15 ns t clch rise time 20 ns t chcl fall time 20 ns
29 at89s53 0787e?micro?3/06 . shift register mode timing waveforms ac testing input/output waveforms (1) notes: 1. ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. timing measure - ments are made at v ih min. for a logic 1 and v il max. for a logic 0. float waveforms (1) notes: 1. for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs. serial port timing: shift register mode test conditions the values in this table are valid for v cc = 4.0v to 6v and load capacitance = 80 pf symbol parameter 12 mhz oscillator variable oscillator units min max min max t xlxl serial port clock cycle time 1.0 12t clcl s t qvxh output data setup to clock rising edge 700 10t clcl - 133 ns t xhqx output data hold after clock rising edge 50 2t clcl - 117 ns t xhdx input data hold after clock rising edge 0 0 ns t xhdv clock rising edge to input data valid 700 10t clcl - 133 ns
30 0787e?micro?3/06 at89s53 notes: 1. xtal1 tied to gnd for i cc (power-down) 2. lock bits programmed
31 0787e?micro?3/06 at89s53 ordering information speed (mhz) power supply ordering code package operation range 24 4.0v to 6.0v at89s53-24ac at89s53-24jc at89s53-24pc 44a 44j 40p6 commercial (0 c to 70 c) 4.0v to 6.0v at89s53-24ai at89s53-24ji at89s53-24pi 44a 44j 40p6 industrial (-40 c to 85 c) 33 4.5v to 5.5v at89s53-33ac at89s53-33jc at89s53-33pc 44a 44j 40p6 commercial (0 c to 70 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 40p6 40-lead, 0.600" wide, plastic dual inline package (pdip) = preliminary information
32 0787e?micro?3/06 at89s53 packaging information 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
33 0787e?micro?3/06 at89s53 44j ? plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.986 ? 16.002 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
34 0787e?micro?3/06 at89s53 40p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 52.070 ? 52.578 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
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